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SMD099 Digital Structures on Silicon 12.0 ECTS credits | |
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TIMEPERIOD: III+IV LANGUAGE:English/Swedish EXAMINER Glenn Jennings Univ lekt PREREQUISITES SMD098 Computation Structures, SMD011, SMD012 or SMD038 Imperative Programming, and SME034 Basic Electronic Engineering or the equivalent. COURSE AIM This course deals with the physical design of very-large-scale digital circuits all the way down to the silicon surface, where the skills required are above and beyond those vested in the synthesis and standard-cell paradigm; for example the design of full-custom high-density circuits on the order of ten million CMOS transistors, and/or nominal operating frequencies on the order of 200 MHz or more. Depending on budget and perhaps on industrial sponsoring, the circuits designed by the students will be fabricated in a suitable sub-micron VLSI technology. This course builds upon the students' knowledge of how to manage the complexity of larger, functionally complex digital systems. CONTENTS Logic synthesis: synthesis of combinational circuits using a cell library; blocks implemented as standard-cell place-and-route modules. Disadvantages of this method with regards to utilization of silicon, and performance of such modules. Switching theory: P and N switches. Static complementary switch networks and their layout; simple switching functions. Geometrically regular switch networks, ROM. Physical Design on Silicon: Review of physical and electronic properties of CMOS technologies. Layers, wires and contacts in CMOS. Layout design rules, regular structures. Layout planning, layout compaction. Automated Layout Generation: modularization and parameterization. Embedded layout languages. Module generators, PLA generators. The static pull-up. Global routing. Silicon compilation. Latch-based design: the disadvantages of flip-flops. Review of the transparent latch; design of static and dynamic synchronisers in silicon. Multiple clock phases, their advantages and their cost. Layout extraction: simulation at transistor and switch levels. Design Rule Checking (DRC). Extraction to gate level; static formal verification of layout against higher-order descriptions. Dynamic logic: charge, memory, precharging. Races in precharged logic. N- and P-blocks, N- and P-synchronisers. Domino logic. True Single Phase Clocking (TSPC). Other: driving large capacitive loads, charge coupling, pads, etc. TEACHING Instruction consists mainly of an obligatory design laboratory, executed in project format and in small groups. Project performance, however, is graded quantitatively. The project is carried out in steps according to a strict timeplan. Via the design project, the student becomes familiar with those design tools required to carry out a complete digital design at the layout level. Lectures and sessions. Written examination checks whether the student has understood the principles behind, and purpose of, the tools used in the project work. EXAMINATION Written examination. Final course grade based on both the written examination and the project: quantitative grade. COURSE GRADE SCALE: U,3,4,5 ITEMS/CREDITS | |
| Project work and report | 9.00ECTS |
| Written exam | 3.00ECTS |
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COURSE LITTERATURE To be determined. Choice of design tool platform (either Mentor Graphics or Cadence) also to be determined. REMARKS Course will not be given during the academic year 98/99. Limited enrollment. The student should have an interdisciplinary attitude, between electronics and programming. SMD099 and SMDxxx (tentatively named "Digital Design by Synthesis") alternate every other year, and both may be taken by the same student. Further information: Glenn Jennings |
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