Engelska Studiehandboken kurser

Computer Science, Electrical Engineering

SMD075 Digital Architecture for VLSI 6.0 ECTS credits

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General information about studying at Luleå university

TIMEPERIOD: III

LANGUAGE: English/Swedish

EXAMINER
Glenn Jennings Univ lekt

PREREQUISITES
Digital Design.

COURSE AIM
The course is designed to give the student foundational competence in methodologies for design of large, functionally complex digital systems where VLSI is available as an implementation technology. Subgoals: - to give the student a basic competence in the design of synchronous digital structures given a problem formulated at a high level. - to acquaint the student with a number of VLSI implementation methods, their possibilities and limitations, and how the design process is adapted for good utilization of VLSI in large designs. - to acquaint the student with different types of modeling techniques and design tools which support the design process from the first evaluations all the way to implemented circuits.

CONTENTS
Architecture and Block Level Design. Explorative structured design methodology. Register transfer level (RTL), compiled simulation. The latch, two-phase clocking, parallelism, pipelining. Static timing analysis, critical paths, clock frequency. Hierarchy and design regularity. Logic Synthesis. Functional descriptions of combinational networks. Tools for two-level and multi-level logic minimization. Mapping to implementation library. Classical state machine languages. Standard cells, mapping/routing for field-programmable technologies (FPLD). Switch Networks and Layout. Simple switch functions. Switch networks with regular layouts. ROM. Charge, memory, precharging. N and P transistors, conductors and contacts in CMOS. Layers, design rules. Floorplanning. Layout sketches and compaction. Circuit extraction and simulation at switch- and circuit-levels. Automated layout, modules and parameterisation. Module and PLA generators. Silicon compilation. Design rule checking (DRC). Silicon's Electrical Properties. The MOS transistor. N- and P-wells, substrate contacts. Resistance and capacitance. Driving of large capacitive loads, pads. Timing verification, clock skew. Power consumption.

TEACHING
Instruction consists of lessions and compulsory assignments performed by students, partly in smaller groups, partly alone.

EXAMINATION
Examination is based partly from passed laboratory work and from a written examination with quantitative grade.
COURSE GRADE SCALE: U,3,4,5

ITEMS/CREDITS


Laboratory work                                             	1.5ECTS
Written exam                                                	4.5ECTS

COURSE LITTERATURE

REMARKS

Last modified : 97-06-05 by Jan Lindberg
Further information: Glenn Jennings

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